Communication Systems Background
In modern digital systems, digital information has to be processed in a reliable and efficient way. In this context, digital information is to be understood as information available in discrete, i.e., discontinuous values. Bits, collection of bits, but also numbers from a finite set can be used to represent digital information.
The efficiency of digital communication systems can be expressed in terms of the time it takes to transfer certain amount of information (speed), the energy that is required to transmit the information reliably (power consumption) and, the number of wires per bit that is required for communication (pin-efficiency). In most systems, several trade-offs exist between these parameters and, depending on the application, some of these parameters may be more important than others. In most chip-to-chip, or device-to-device communication systems, communication takes place over a plurality of wires to increase the aggregate bandwidth. A single or pair of these wires may be referred to as a channel or link and multiple channels create a communication bus between the electronic components. At the physical circuitry level, in chip-to-chip communication systems, buses are typically made of electrical conductors in the package between chips and motherboards, on printed circuit boards (“PCBs”) boards or in cables and connectors between PCBs. In high frequency applications, microstrip or stripline PCB traces may be used.
Common methods for transmitting signals over bus wires include single-ended and differential signaling methods. In applications requiring high speed communications, those methods can be further optimized in terms of power consumption and pin-efficiency, especially in high-speed communications. [Slepian] suggested the use of permutation codes for transmission of information on communication channels in which signals are disturbed by Gaussian noise. More recently, practical vector signaling methods based on Permutation Modulation Codes, Sparse Modulation Codes or Superposition Signaling Codes, as taught by Cronie II, SPM and SUPM respectively, have been proposed to further optimize the trade-offs between power consumption, pin efficiency and noise robustness of chip-to-chip communication systems. In those vector signaling systems, the digital information is transformed into a different representation space in the form of a vector codeword, CW, that is chosen in order to optimize the power consumption, pin-efficiency and speed trade-offs based on the transmission channel properties and communication system design constraints. Herein, this process is referred to as “encoding”. At the receiver side, the received signals corresponding to the codeword CW are transformed back into the original digital information representation space. Herein, this process is referred to as “decoding”.
FIG. 1 represents a high-level block diagram of a prior art communication system. At the transmit unit 100 side of the communication system, an encoder 110 transforms a sequence of k information symbols 105 into a vector codeword CW. A driver 120 maps vector codeword CW into a set of physical signals and transmits them on the n wires 135 of bus 130. Although FIG. 1 shows a number of lines for the k information symbols 105 and a number of wires 135, it should be understood that different values for k and n could be used and they need not be equal.
At the other side of bus 130, a receive unit 140 maps the n received physical signals from wires 135 back into k information symbols 145. Receive unit 140 comprises a bus receiver in the form of a signal-to-digital converter (“SDC”) 160 and a vector codeword decoder (“DEC”) 170. In FIG. 1, a task of the SDC 160 is to reconstruct an estimate of the transmitted vector codeword CW from the analogue signals transmitted and recorded over the n bus wires 135. SDC 160 then transmits the estimate of vector codeword CW to codeword decoder 170. Codeword decoder 170 can then reconstruct the k output bits by applying the reverse transformation from that of transmit encoder 110. SDC 160 is shown comprising a sampler 180 and a rank-order unit 190.
As an example, bus 130 might be a bus between a processor and memory. In that case, the physical wires may take the form of striplines or microstrips on a PCB. Another example of bus 130 might be a set of wires connecting two different devices. The system of FIG. 1 may also be extended to bi-directional communication settings. In general, the information symbols may be bits, but other digital representations of information symbols as described above are also permissible.
Memory Systems Background
Common methods for storing digital information into volatile memory such as dynamic random-access memory (“DRAM”), as well as non-volatile memory such as flash memory (“Flash”) or phase change memory (“PCM”), require physically storing the digital information in cells as a single or multilevel charge or material phase.
In general, when the charge or phase reaches its maximum level, it cannot be increased anymore so the cell needs to be erased back to the lower charge or phase value before it can store a new value, which has significant impact on the memory efficiency, reliability and lifetime with the current technologies. To address those issues, differential vector storage schemes have been recently proposed, as taught for instance by NVM, to further minimize the number of memory cell erasure cycles while enhancing the reliability and writing speed of memory systems.
Similarly, in the case of volatile DRAM, each bit of digital information is typically stored into a capacitor. Capacitors leak charge over time and therefore require periodic refresh to compensate for charge leakage, which has significant impact on the power consumption required to maintain the memory information suitable for reliable reading. To address those issues, differential vector storage schemes have been recently developed to further minimize the number of DRAM refresh operations as described and/or illustrated in, for example, NVM.
FIG. 2 represents a high-level block diagram of a generic memory system comprising a controller 200 a page read-write module 210, and a number of R/W modules 220 in charge with handling a set of individual memory cells or capacitors 230. In various memory systems, the page read-write module 210 further comprises, for each R/W module 220, a write encoder 240 and a read decoder 250. Read decoders 250 are shown including rank-order units 290.
Vector Processing Background
In this disclosure, we refer collectively to the methods disclosed in Cronie II, SPM, SUPM, NVM and similar extensions as “vector processing” methods.
In a system according to FIG. 1, in accordance with the vector signaling teachings of Cronie II, SPM and/or SUPM, at the transmitter side, in transmit unit 100, encoder 100 might comprise a vector signal encoder and driver 120 might comprise a bus driver. Transmit unit 100 processes the sequence of k information symbols 105 in a period T and thus takes in k new information symbols per period T. In preferred embodiments, T is substantially smaller than one second and transmit unit 100 can transmit the information content of k/T symbols per second. In the l-th time interval of T seconds, the vector signal encoder maps these k bits to a vector CWl of size n. During the l-th symbol period of T seconds, the bus driver generates the vector s(t) of n continuous signals, s1(t) to sn(t), for each of the n bus wires 1, . . . , n in bus 135 as:s(t)=CWl*p(t)
where p(t) is a pulse shape signal.
Various vector signal encoders may be applied, where the vector CWl may be a codeword from a permutation modulation code, a sparse signaling code, a superposition signaling code, or another code of a vector signaling method. For instance, the methods taught by Cronie II, SPM and/or SUPM respectively may be used, as well as other similar methods known to those skilled in the art, such as, for instance, the permutation modulation codes disclosed in [Slepian], or the signaling methods of [Cornelius] or [Poulton]. A permutation modulation code or sparse signaling code CWl is defined by a basis vector, x0, where the code consists of all permutations of x0. For the sake of illustration, we assume that the entries of x0 are sorted in descending order, but other embodiments are also possible.
At the receiver side, a vector signal v(t) is received, which may be an attenuated version of the original vector signal s(t). Typically the channel response is frequency selective, which may lead to inter-symbol interference (“ISI”). Furthermore, noise may be added to the transmitted signal, for instance, Gaussian noise.
Without loss of generality, we assume that the receiver observes the received vector signal v(t) at some sampling time t0 and we denote the resulting signal values by v. Sampler 180 can be a front-end sampler that samples the received vector signal y(t) at sampling time t0 to generate the vector of samples v. In prior art systems with reference to FIG. 1, the sampled vector v is further input into rank-order unit 190.
The rank-order sorting operation may determine a full ordering of the sampled values on the wires or a partial order. A full ordering would mean that all values on the n wires are sorted. A partial ordering would mean that only a subset of the wires are determined that carry some of the largest and some of the smallest values, which is enough when the other values are non-quiescent, in particular in the case of a sparse modulation code.
As an illustration of a partial sorting application, in the 8b8w signaling plotted in FIG. 1 as taught by SPM where the basis vector x0 is defined as:x0=[1 1 0 0 0 0 −1 −1],the output of rank-order unit 190 may only comprise four indices 195 on four wires/channels/etc. indicating the ranking of the wires where respectively the two largest (+1, +1) and the two smallest sample values (−1, −1) have been measured. Indeed, in the “8b8w” case, the four other wires' samples have a zero value and are quiescent.
Possible detailed embodiments of rank-order units 190 and codeword decoder 170 have been taught in SPM. For instance, in some embodiments, rank-order units 190 may further comprise a max-detector unit to select the largest (positive) values and a min-detector unit to select the smallest (negative) values out of the n components of the sampled y vector signal.
An example of a sampled vector signal may be:y=[1.1 0.2 −1.3 0.19 −0.9 0.01 −0.3 1.2 ]where the largest value 1.2 is detected on wire 8, the second largest value 1.1 is detected on wire 1, the smallest value −1.3 is detected on wire 3 and the second smallest value is detected on wire 5. The remaining elements are treated as corresponding to zero values.
Codeword decoder 170 can then reconstruct the original vector CWl as:CWl=[1 0 −1 0 −1 0 0 1]
Codeword decoder 170 can then further reconstruct the k output bits 145 by mapping back vector CWl into the initial representation space, by applying the reverse operation of encoder 110.